The present invention relates to a high-density semiconductor device and a manufacturing method thereof, and more particularly to a high density semiconductor device having a self-aligned contact structure, and a method for manufacturing the same.
Recently, along with the trend toward attaining ultra-high density in semiconductor memory devices, the contact area has been decreased for inter-layer contacts or metal interconnections. Accordingly, the aspect ratio (depth-to-diameter) of the contact hole has increased 1.5 times, which in turn increases the defect rate caused by contact failures within the narrow and deep contact holes.
In a 16 Mbit SRAM of Yamanaka presented in IEDM90, pp. 477-480, the nest contact size is 0.4 .mu.m.times.0.4 .mu.m. Additionally, in a 64 Mbit DRAM of Kawamoto presented in Symposium on VLSI Technology, 1990, pp. 13-14, a 0.3 .mu.m design rule is used and a method for forming a buried bitline contact hole self-aligned in the word line is disclosed. That is, in a high-density semiconductor device using a design rule below one-half micron, a contact hole is opened by a self-aligning method using anisotropic etching instead of the conventional photolithography process. Also, a selective silicon growth method is used to form a contact pad, or a low-resistance bitline is formed using a polysilicon planarization technique.
However, according to the selective silicon growth technique of Yamanaka, after forming a self-aligned contact, silicon is selectively grown and then the planarizing process of the following inter-insulating layer is carried out, making the process overly complicated. Moreover, due to the selective silicon growth, the manufacturing cost is increased and micro-bridging occurs. Furthermore, in the polysilicon planarizing technique of Kawamoto, after a polysilicon layer is thickly formed, its surface is planarized by an etch-back process, a refractory silicide layer such as WSi.sub.2 is deposited thereon, and then a bitline pattern is formed by the photolithography process. Therefore, a stringer is generated by the unremoved polysilicon left along the groove of downward stepped portion of the insulating layer.
To specifically describe the problems of the conventional technique, the contact formation process of a conventional SRAM will be described with reference to FIGS. 1A through 1F.
Referring to FIG. 1A, a gate oxide layer 3, a gate electrode layer 5, and a first insulating layer 7 of a high temperature oxide (HTO) are sequentially formed on a semiconductor substrate 1. Then, a photoresist is coated on first insulating layer 7, and a photoresist pattern 9 is formed by a photolithography process, using a gate electrode pattern mask.
Referring to FIG. 1B, first insulating layer 7 and gate electrode layer 5 are selectively etched using photoresist pattern 9 as a mask, thereby forming the gate electrode pattern. Thereafter, a low-density impurity region 10 which is self-aligned with the gate electrode pattern is formed in semiconductor substrate 1, and photoresist pattern 9 is removed. Then, a second insulating layer 11, e.g., an HTO layer, is deposited on semiconductor substrate 1.
Referring to FIG. 1C, second insulating layer 11 is anisotropically etched to form a first gate sidewall spacer 11' only on the sidewalls of the gate electrode pattern, and a high-density impurity region 12 which is self-aligned with first gate sidewall spacer 11' is formed in semiconductor substrate 1. Successively, a third insulating layer 13 of an oxide layer is deposited on semiconductor substrate 1. After that, a photoresist is coated on third insulating layer 13, and an opening 15 is exposed in the photoresist via a photolithography process, using a mask for forming a contact hole pattern.
Referring to FIG. 1D, a contact hole is opened by the anisotropic etching of third insulating layer 13 which is exposed via opening 15. At this time, a second gate sidewall spacer 13' of third insulating layer 13 is formed on first gate sidewall spacer 11'.
Referring to FIG. 1E, after removing the photoresist, first conductive layer 20 composed of polysilicon 17 and refractory metal 19, respectively, are deposited on semiconductor substrate 1. Then, first conductive layer 20 is covered with a photoresist, and photoresist pattern 21 is left only where a contact pad will be formed via photolithography process, using a mask for forming contact pad pattern.
Referring to FIG. 1F, first conductive layer 20 is anisotropically etched using photoresist pattern 21, then contact pad 20' composed of upper pad 17' and lower pad 19' is left only under the photoresist pattern 21. At this time, residual layers 17" and 19" which are the remaining material of the first conductive layers, remain along a groove 4 formed in the downward stepped portion of third insulating layer 13. These residual layers 17" and 19" extend along groove 4 and form stringers, and thus provide an electrical path between metal interconnections formed thereon, causing shorts. This increases the defect rate and degrades the reliability of the device.
Therefore, to remove such residual layers 17" and 19", the first conductive layers are over-etched during anisotropic etching. However, the conductive residue within the groove is difficult to completely eliminate.